and there should be few 805x-specific doubts remaining.

As for Cyrille's 6502, it should be noted that there's no separation between code and data space on this microPROCESSOR (No ROM, No RAM, No I/0, no SFR's) and that it has only a single R/w line rather than a separate nRD and nWR.

Those two signals are best generated by NANDing the 6502's PHASE-2 output with R/w in order to create the latest possible enable to the device to be read. nWR can be created by inverting R/w and NANDing the result with the PHASE-0 input, which helps provide ample data-hold time, as required by some devices. One could invert Phase-0 and OR it with R/w, which would provide very slightly better timing, but that's not required.

Memory address decoding, i.e. chip-select creation works just as it does with the 805x, keeping in mind that there's no data/code separation and there's no need for demultiplexing the low addresses and data.

RE