??? 03/26/06 01:40 Modified: 03/26/06 01:42 Read: times |
#113111 - Reason of buffering Responding to: ???'s previous message |
Zeeshan said:
I suppose a 74HC244 will be adequate to buffer /RD, /WR, A0 and A1 lines? The idea behind the buffering of /RD and /WR lines is, that these lines are most of the time pulled high by only the weak internal pull-up. So, source impedance (about 10...50kOhm) is much higher than the typical 50Ohm of a 74HCMOS output. This results in an increased susceptibility of /RD and /WR lines against charge injection via stray capacitance, means signal integrity on these lines can easily be eroded. Have a look at /RD and /WR pins of the RAM chips to find out, whether these signals are proper or not. Kai |