I think you need to do some arithmetic. The AT89c52 has a datasheet that characterizes the Iol and Ioh of the ports and the databook on whatever logic family you use for latching/buffering the addresses will give you the same figures for the external logic. If you add up all the capacitances including the capacitance of the wires you're using, then you'll have some idea of how much the propagation delays of those signals will be impacted due to loading, both resistive and capacitive.

You'll find, I think, that the capacitance is of significance, and the DC loading is not.

The capacitance will lead you to a delay in the settling time of those signals that are critical, and from that you can determine whether you need buffering. The old NMOS 8052 was not able to source/sink much current, while the CMOS parts are more able.

Keep in mind, what you're fighting is delay, not current, though it really is the charge current of the stray capacitance together with the input capacitance of the driven devices that comprises the delay. If, through the output impedance of your MCU you can charge all the load capacitance and stray capacitance, then you need no buffer. The buffer, after all, interoduces another ~10 ns of delay.

RE