Oh dear, that's an absurd idea! Two failing memory accesses do not make one proper one. That's really absurd! Use a 7.3728MHz crystal!

There's another mistake in your circuit: If /RD goes low, U14 AND some other chip, memory chip U4 or U5 for instance, will emit data on the data bus, resulting in a bus contention!!! You will never read something useful from these memory chips with this configuration!

Also, I would buffer /RD and /WR lines and would use a MAX1232.

Kai