Well Eric,

-> 1 X 8K SRAM (@ 0000h ~ 1FFFh)
-> 1 X 32K SRAM (@ 2000h ~ 9FFFh)
the decoding is so much easier if you make it
-> 1 X 8K SRAM (@ 8000h ~ 9FFFh)
-> 1 X 32K SRAM (@ 0000h ~ 7FFFh)

If u look at the address decoder schematic that i have just posted, it is not much difficult to implement what u suggest, and neither what i have already implemented. Yes, i know this is a damn legacy decoder, could have been implemented in a GAL or PLD; and most probably it will be implemented in a GAL on the final PCB board. Its here for the wire wrap simple design.

why
-> 1 X 32K FLASH ROM (@ 0000h ~ 7FFFh)
the 89.. chips have internal code flash

Well, the board CURRENTLY uses 89 chip, but by placing an external flash / eeprom, it will give students more flexibility if they wanted to place in a 8052 part.

Well, i was initially planning on using a 89c2051 device for capturing and expanding teh external multiple interrupts of the classic 8052, but i had to go for the 8259 part since i presume students will be more familiar with.

Well, i needed over 50 output line and approximately another 24 for input, so if i place single chips, they would quickly eat up the circuit-baord real estate and then i will also have bus contention problems. Hence, i am presently using 2 8255s, and i will add another 8255 in the final stages. This once chip gives me 24 lines, and they are programmable to be inputs as well as outputs.

Well, yes KBD and Display can be used by aux IO ports, but then the controller will have to scan the keyboard matrix as well as the display refresh. Good for student level, but if this system is supposed to sequence a lot of operations of a machine, then this will be a problem. Hence teh 8279.