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???
03/15/06 18:21
Modified:
  03/15/06 18:29

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#112257 - a multiple-post Re to Erik
Responding to: ???'s previous message
> ... formatting ...
Sorry, I found out what you meant only now... end of pre tag missing... sorry...

> ... speed penalty...
Well, reading of '51 softcores, they usually mention speed and area penalty if the (JTAG) debugging facility is included. I don't know how it is valid for a dedicated chip, but I bet there might be some for the SiLabs, too. Of course, it might mean that it works up to 110MHz instead of 120MHz without it, so in fact it does not matter.

You are right, we can erase that line...

> ... wiki and #$%^....
OK call it a collectively-written FAQ (or at least collectively-writeable). The trouble is it is far away and cumbersome. If it would be here, a click away, I am 100% it will come alive.


> ...negative OR...

Well, this is something I was taught is called OR in negative logic. Negative OR is a NOR for me in positive logic. But, if you want to implement it, you will get a 74xx implementing AND (OK, if it should be out of the drawer, then two gates from a 74..00 :-)))

> ...download update w/o disconnect...
Sorry I misunderstood - update to the debugging facility (monitor, here) you meant, didn't you? Well, if the monitor is in (EP)ROM, there is no way to update is it? If it itself sits or can sit in a RAM, theoretically it is possible to update, but not feasible...
Updating/downloading the application... I think most of the monitors do (in fact, some of them don't do anything else... :-(



Jan Waclawek



List of 49 messages in thread
TopicAuthorDate
MONITOR for ASIC with 8051 IP core            01/01/70 00:00      
   replacing serial by xxx            01/01/70 00:00      
   JTAG?            01/01/70 00:00      
      should have come to me            01/01/70 00:00      
      JTAG money talks...            01/01/70 00:00      
         shome mishtake sureley            01/01/70 00:00      
         External UART            01/01/70 00:00      
      JTAG != debug port            01/01/70 00:00      
         Debug via JTAG            01/01/70 00:00      
            Does it make sense?            01/01/70 00:00      
            debugging            01/01/70 00:00      
               a readable version of the above            01/01/70 00:00      
                  coments            01/01/70 00:00      
                     won't we make it a separate thread?            01/01/70 00:00      
                        screw the wiki, who but you have been th            01/01/70 00:00      
   ASIC as in ASIC or FPGA?            01/01/70 00:00      
      How can I forward to other interface?            01/01/70 00:00      
         stick an IIC port on            01/01/70 00:00      
         what is not clear?            01/01/70 00:00      
            re: replacing setial by xxx            01/01/70 00:00      
               von Neumann RAM            01/01/70 00:00      
                  I get it...I'll have to play with FlashM            01/01/70 00:00      
                     IAP, ISP, von Neumann and others            01/01/70 00:00      
                        STOP, ! it is NOT            01/01/70 00:00      
                           NOR?            01/01/70 00:00      
                              oh well, wrong again            01/01/70 00:00      
                                 a multiple-post Re to Erik            01/01/70 00:00      
                                    replies            01/01/70 00:00      
               von Neumann RAM            01/01/70 00:00      
         Sure about the volume?            01/01/70 00:00      
            There is something VERY strange here: T            01/01/70 00:00      
               indeed VERY strange            01/01/70 00:00      
                  could it be            01/01/70 00:00      
                     maybe            01/01/70 00:00      
                  Mea culpa ! WRONG EXAMPLE!            01/01/70 00:00      
                     Then use DEDICATED ASICS            01/01/70 00:00      
                        One more detail just to get it right            01/01/70 00:00      
                           You haven't done the homework yet            01/01/70 00:00      
                     For that qty modify a standard chip            01/01/70 00:00      
                  Orders of Magnitude            01/01/70 00:00      
                     Re: Orders of Magnitude            01/01/70 00:00      
                        That may be a good per-piece cost            01/01/70 00:00      
   missing details            01/01/70 00:00      
      this is just a joke            01/01/70 00:00      
         ASIC size            01/01/70 00:00      
      Still price consideration problems            01/01/70 00:00      
   now paralell posted            01/01/70 00:00      
      End result and solution!            01/01/70 00:00      
         wrong sorry            01/01/70 00:00      

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