| ??? 03/15/06 01:08 Read: times |
#112200 - Debug via JTAG Responding to: ???'s previous message |
Jan Waclawek said:
JTAG is NOT a debug port. I didn't say it was. I carefully said, "debug via JTAG" - which I think is quite precise, accurate, and succinct? it is senseless waste of resources (unless you need real boundary scan interface... In developing an ASIC, isn't it quite likely that you will actually need a real boundary scan interface?! The cutting edge is single-pin debugging (see e.g. Atmel AVR, Zilog Z8). Plenty of AVRs use their JTAG port to access the on-chip debug. But, again, it's just an interface: the point is that they have debugging hardware on-chip - they don't mess about with stone-age Monitor technology! With a separate microncontroller chip (AVR, Z8, 8051, whatever) you still have the chance to probe on the processor pins. With an IP core buried deep inside an ASIC you have no such access. But the debug hardware which supports the internal "hooks" would need to be implemented anyway, so the cost of it (as silicon area as well as design cost) remains the same. I can see that the incremental cost of the debug hardware could be noticeable in relation to an AVR or 8051 microcontroller, but is it really going to be significant in the scale of a whole ASIC?! The monitor is cheaper, although provides less luxury for debugging. See above. If this is the only debug access you have, you will soon realise that it was not just a "luxury"... |
