Thanks guys for the info, I try to answere the questions:

First of all, we are dealing with a development of a real ASIC not an FPGA, or to be more exact we are giving the spec. to a company who will construct the ASIC using an 8051 IP core.

The more features we want the bigger the ASIC will.

Smith, it is so: we are planning to use this chip for different applications for some very simple one where we will have a simple software (that can be written without any advanced debug possibilities) and also for quite complicated things where we need some debug power.
And for example if you sell 1000 chip for applications where you don't realy need an UART and a JTAG which raises the costs of the ASIC chip by 1$ than you wasted already 1000$.

One more question Andy (it will sound silly):
The only thing I have a problem with that I don't have the FlashMon51 source code therfore I can't imagine how it is sending the data to the external-uart.

Could it be so that this monitor program simple sends data bits (which would originaly be placed to the UART buffer) to the P1 port?
If it is so, than in the IP core would it be possible simply forward these data bits for example to an SPI buffer? Or do I underestand the whole concept wrong?

And one last (also sily) question just to be sure:
In the Keil pages it is written that to use FlashMon51 the MCU should support In-Application Programmable (IAP) Flash memory. I guess ISP is not the same than IAP. That means IAP has to be suppeted by the core? Is there any specification how should be an IAP implemented on the IP core (or at least the ROM commands?) I couldn't find anything on the net.

Thanks a lot again for your answeres.

Greetings

Attila