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???
03/15/06 13:24
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#112224 - coments
Responding to: ???'s previous message
Serial ISD requires to have the "vehicle" (the "serial port"), and physical "connections" to all the resources inside the chip. This means some chip area increase, and also some speed penalty, as the "key points" have to be tapped at various points of the core and brought out usually to the chip's edge where the "extra" circuitry would sit.
look at SILabs, no "speed penalty", the "brought out" are "programming pins" needed anyhow.

I expand your table
Summary of pros (+) and contras (-):
                                               low cost high cost
                             serial ISD monitor   ICE       ICE
extra chip area needed            -        +       -         -       
speed penalty                     -        +	   -         -
interrupt occupied                +        -	   +-        -
RAM/stack/code space occupied     +        -	   +-        -
vonNeumann code space needed      +        -	   *         *
single stepping, stop&run         +        +	   +         +
resources inspection              +        +	   +         +
breakpoints                       +        -	   +         +
conditional breakpoints           -        -       -         +
traces                            -        -	   -         +
PC application needed             v        +-	   v         v
correctable                       -        +	   +         +
download update w/o disconnect    +        ?       +         +
pins occupied                     +-       -	   -         -
various interface possible        -        +	   n/a       n/a
* irrelevant, the on chip memory is emulated
v needed, but included in delivery

Jan what does "correctable mean?
a romulaor user please add a column
someone please fix '?' in tyhe monotor column

a comment: The Ceibo low cost emulators for the Philips pre SoftICE chips use some built in functions in the standard chips and are thus "universal for all", you just pop the chip out and insert another Philips derivative.

Other emulators low or high cost use bondout chips and do thus need an additional "pod" if you want to emulate another derivative

Erik







List of 49 messages in thread
TopicAuthorDate
MONITOR for ASIC with 8051 IP core            01/01/70 00:00      
   replacing serial by xxx            01/01/70 00:00      
   JTAG?            01/01/70 00:00      
      should have come to me            01/01/70 00:00      
      JTAG money talks...            01/01/70 00:00      
         shome mishtake sureley            01/01/70 00:00      
         External UART            01/01/70 00:00      
      JTAG != debug port            01/01/70 00:00      
         Debug via JTAG            01/01/70 00:00      
            Does it make sense?            01/01/70 00:00      
            debugging            01/01/70 00:00      
               a readable version of the above            01/01/70 00:00      
                  coments            01/01/70 00:00      
                     won't we make it a separate thread?            01/01/70 00:00      
                        screw the wiki, who but you have been th            01/01/70 00:00      
   ASIC as in ASIC or FPGA?            01/01/70 00:00      
      How can I forward to other interface?            01/01/70 00:00      
         stick an IIC port on            01/01/70 00:00      
         what is not clear?            01/01/70 00:00      
            re: replacing setial by xxx            01/01/70 00:00      
               von Neumann RAM            01/01/70 00:00      
                  I get it...I'll have to play with FlashM            01/01/70 00:00      
                     IAP, ISP, von Neumann and others            01/01/70 00:00      
                        STOP, ! it is NOT            01/01/70 00:00      
                           NOR?            01/01/70 00:00      
                              oh well, wrong again            01/01/70 00:00      
                                 a multiple-post Re to Erik            01/01/70 00:00      
                                    replies            01/01/70 00:00      
               von Neumann RAM            01/01/70 00:00      
         Sure about the volume?            01/01/70 00:00      
            There is something VERY strange here: T            01/01/70 00:00      
               indeed VERY strange            01/01/70 00:00      
                  could it be            01/01/70 00:00      
                     maybe            01/01/70 00:00      
                  Mea culpa ! WRONG EXAMPLE!            01/01/70 00:00      
                     Then use DEDICATED ASICS            01/01/70 00:00      
                        One more detail just to get it right            01/01/70 00:00      
                           You haven't done the homework yet            01/01/70 00:00      
                     For that qty modify a standard chip            01/01/70 00:00      
                  Orders of Magnitude            01/01/70 00:00      
                     Re: Orders of Magnitude            01/01/70 00:00      
                        That may be a good per-piece cost            01/01/70 00:00      
   missing details            01/01/70 00:00      
      this is just a joke            01/01/70 00:00      
         ASIC size            01/01/70 00:00      
      Still price consideration problems            01/01/70 00:00      
   now paralell posted            01/01/70 00:00      
      End result and solution!            01/01/70 00:00      
         wrong sorry            01/01/70 00:00      

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