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???
03/15/06 00:22
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#112193 - missing details
Responding to: ???'s previous message
Maybe using some proprietary serial communication scheme isn't the smartest way to do this. I'd say this should be obvious to everyone. Consequently, I conclude that there's a really compelling reason to do that.

What is it?

Nearly every ASIC supplier with whom I've had contact includes JTAG as a means for testing as well as a debugging tool for their products. If you choose not to use that, it's your choice, but it's to your advantage to do so, however, inconvenient and awkward it may prove to be. You can certainly debug and test with JTAG, so it's a vehicle you shouldn't ignore.

Why don't you want to use the "default" internal UART? You can include as many of them as you like, so an external one or an internal one will behave more or less the same, depending on how you build your ASIC.

If you'd spent 5 minutes searching the web for 8051 monitor, you'd have a list of at least a dozen of them. I did that and found plenty. You should do this yourself, though, so you get an idea of how foolish not searhcing first makes you appear to be.

You need, perhaps, to be more specific about just what you mean by ASIC. To many of us, that means a custom-built hard-logic circuit made to order for us in a silicon foundry. I've not been involved in such projects since the '80's, aside from FPGA-to-ASIC migrations. If you're "up" to such a task, you must have at least $2 million U.S. for startup, licensing, and foundry charges, as well as software tools, and you need a team of long-experienced engineers to accomplish the task, which will take, typically, about a year.

It's not something you're going to pull off in your back bedroom next weekend.

RE




List of 49 messages in thread
TopicAuthorDate
MONITOR for ASIC with 8051 IP core            01/01/70 00:00      
   replacing serial by xxx            01/01/70 00:00      
   JTAG?            01/01/70 00:00      
      should have come to me            01/01/70 00:00      
      JTAG money talks...            01/01/70 00:00      
         shome mishtake sureley            01/01/70 00:00      
         External UART            01/01/70 00:00      
      JTAG != debug port            01/01/70 00:00      
         Debug via JTAG            01/01/70 00:00      
            Does it make sense?            01/01/70 00:00      
            debugging            01/01/70 00:00      
               a readable version of the above            01/01/70 00:00      
                  coments            01/01/70 00:00      
                     won't we make it a separate thread?            01/01/70 00:00      
                        screw the wiki, who but you have been th            01/01/70 00:00      
   ASIC as in ASIC or FPGA?            01/01/70 00:00      
      How can I forward to other interface?            01/01/70 00:00      
         stick an IIC port on            01/01/70 00:00      
         what is not clear?            01/01/70 00:00      
            re: replacing setial by xxx            01/01/70 00:00      
               von Neumann RAM            01/01/70 00:00      
                  I get it...I'll have to play with FlashM            01/01/70 00:00      
                     IAP, ISP, von Neumann and others            01/01/70 00:00      
                        STOP, ! it is NOT            01/01/70 00:00      
                           NOR?            01/01/70 00:00      
                              oh well, wrong again            01/01/70 00:00      
                                 a multiple-post Re to Erik            01/01/70 00:00      
                                    replies            01/01/70 00:00      
               von Neumann RAM            01/01/70 00:00      
         Sure about the volume?            01/01/70 00:00      
            There is something VERY strange here: T            01/01/70 00:00      
               indeed VERY strange            01/01/70 00:00      
                  could it be            01/01/70 00:00      
                     maybe            01/01/70 00:00      
                  Mea culpa ! WRONG EXAMPLE!            01/01/70 00:00      
                     Then use DEDICATED ASICS            01/01/70 00:00      
                        One more detail just to get it right            01/01/70 00:00      
                           You haven't done the homework yet            01/01/70 00:00      
                     For that qty modify a standard chip            01/01/70 00:00      
                  Orders of Magnitude            01/01/70 00:00      
                     Re: Orders of Magnitude            01/01/70 00:00      
                        That may be a good per-piece cost            01/01/70 00:00      
   missing details            01/01/70 00:00      
      this is just a joke            01/01/70 00:00      
         ASIC size            01/01/70 00:00      
      Still price consideration problems            01/01/70 00:00      
   now paralell posted            01/01/70 00:00      
      End result and solution!            01/01/70 00:00      
         wrong sorry            01/01/70 00:00      

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