Well, your decoder is incomplete.

The RAM select is for an 8K block, which is what you want, I guess. The FLASH is four such blocks. Your second RAM is the same four blocks as your FLASH. I assume you use nPSEN to qualify the FLASH. How do you enable your second RAM? There appears to be a level of logic missing.

Also, I see no disposition of A11 and A12. That may not be necessary, but it is redundant decoding of I/O in memory space you may need some day. You could reduce the number of logic levels by using a 74LS145 rather than the '138 on U11. That's open-collector and allows you to tie the four outputs together rather than ANDing them. It will save a few nanoseconds and will be "cleaner." It will, of course, require a pullup resistor at each input. Another possibility is to use the 'HC154, which is a 24-pin 0.300" wide DIP if you're wire-wrapping. Then, of course, you'd need the LS21's again, though I'd recommend HC versions in all cases.

I don't see much wrong with the I/O board with the exception that you could probably simplify and reduce the cost of the thing by using programmable logic. It looks doable, but the old NMOS LSI's don't drive very hard and need external buffers, while a CPLD wouldn't.

RE