It's an old article, stating

"
A 50x Speedup
Dallas Semiconductor has made a good business of clean-room 8051 designs that push the 8051's speed limits. Its newest version, the DS89C420, delivers a 50-MIPS, which is a 50x speedup over the old 12-MHz, 12-stage 8051. Running at 50 MHz, it executes an 8051 instruction in a single clock cycle. Moreover, it offers a full redesign, one that implements the 8051 ISA with modern RISC-like technology. The 8051's sequential 12-stage execution model was transformed into a 4-stage pipelined architecture that delivers apparent 1-cycle instruction execution.
"
Which dates the article back to 2001 or so, before they (Maxim/Dallas) realized that their flash process couldn't manage the fast access time required to reach that rate.

However, I think that same 4-stage pipeline is in the original 805x. With a 4-phased version of the input clock, they can drive their logic and still get everything done on schedule. I haven't observed any pipleline delays that are grossly different from what's observable on the 805x 12-clocker, allowing for cycles to be defined by ALE rather than the clock. More exhaustive examination may happen ... eventually ...

RE