What I'm after is the items to which you refer in the doc's. I've looked at those doc's, too, and have never gotten the impression that the Dallas "ultra" high-speed MCU's are pipelined to any greater extent than the standard 805x core. You're right, of course, in that it would seem likely if not essential that it be pipelined in order to achieve the performance level they advertise.

If you have some specific example, or some specific reference, on which you base your assumption that there's extensive pipelining, I'd like to investigate it, as time allows, just as an exercise in clarifying the already quite muddy waters.

I'm assuming that your caution about pipleline-induced reduction in performance due to stalls resulting from branch not taken, interrupts, or other such conditions is because you figure it is a proprtionally greater delay than one would encounter with a standard core.

Perhaps you're right, but until it's investigated thoroughly, it will remain folklore. If you have an example of a code sequence that you think will be proportionally longer than in a standard 805x, perhaps it will be worth giving it a try and taking a pictuer with a logic analyzer. I don't think it would be particularly burdensome to give that a try.

Nobody expects the DS89C4x0 series to perform at exactly 12x the rate of the 805x, just as nobody expects the standard 805x to execute code at 1 MIPS when operated at 12 MHz. It's hard to execute code using only one-byte instructions. With a single-clocker, each multi-byte instruction takes significantly longer than a single byte instruction, just as you'd anticipate. If you think the mfg's claim is grossly exaggerated, then let's explore this fact with some empirical testing. If you have a code sequence that you think will be a great deal slower than it would be on a standard 805x core, scaled to the clock, of course, then let's give it a look.

RE