I'd be really interested in knowing just where this notion of extensive pipelining comes from, particularly since you state it's apparent from the timing. Please share with us the details of the timing that persuade you that there's pipelining in this architecture that's absent from the "normal" 805x. I have personally observed none of this, not from reading the datasheet and user guide and not from looking at the system timing when it's in operation.

Now, it's quite natural that there are some instructions that, despite the single-clock instruction timing, require more than a single clock tick to complete, first, because they require the fetch of multiple bytes (suggesting it's not pipelined), and also because there are operands in memory, each access to which requires another bus cycle, since it has to stroke memory. A "normal" 805x behaves in the same way, unless I miss my guess.

RE