Sasha's comments where very interesting especialy the part about the stretch cycles'What would be nicer, however, would be a hardware mechanism for mapping stretch cycle counts onto particular XDATA address ranges. Thus, whenever you make an external memory access to an address associated with a slow peripheral, the appropriate number of stetch cycles would automatically be used.'
Obviously this would be achievable with some suitable PLD with a look up table mechanism and variable length delay chains.

And also this comment

You might be running at "12x the 'normal' rate", but in reality, you can never realize a 12x performance increase by switching from a conventional architecture chip to this device. As you can see from the Ultra-High-Speed Flash Microcontroller User's Guide, in the subsection "Comparison To the 8051" beginning at the bottom of p. 52, for any given opcode, the DS89C4x0 offers performance advantage factor of significantly less than 12 for a large number of instructions and opcodes.

This is due to the fact that when a pipelined achitecture processor makes a jump in program execution for whatever reason,be it an interrupt or a branch so the code execution is non-linear the pipeline has to be flushed all the instructions which were partly through the pipeline dicarded and the pipeline has to refill with the new instructions.So any speedup achieved by using a pipeline is only aplicable when executing linear sections of code, your milage will vary according to your application.