Richard,

I've never thought of the DS as implementing pipelining, in the sense typical of say array processing, at all.

As conditionals are now assymetric, it's clear that the old equal clock state machine is gone. Perhaps this has fed a legend of pipelining where the assymetry is assumed to be "flush" timing. Since the core executes at clock speed (or a DPLL fraction) it's pretty clear that it's not a micro-coded machine, anyway.

regards,
p