| ??? 01/31/06 19:33 Read: times |
#108828 - If you want to get really silly Responding to: ???'s previous message |
Depending on what hdl compiler you are using you can generate test vectors which are inputs designed to expose every concievable fault condition for your design but you do tend up with a hge number of test vectors and for a 68000 core design we did we ended up with over 4 million test vectors which took over a week of continious computer time to run on a 2.4 Ghz machine.Not many design teams have that amount of time to spare which is where the problems start. |
| Topic | Author | Date |
| Stress testing a synthetic 8051 core | 01/01/70 00:00 | |
| How about this one? | 01/01/70 00:00 | |
| test suite | 01/01/70 00:00 | |
| Taa daa!!! | 01/01/70 00:00 | |
| although.. | 01/01/70 00:00 | |
| link.. | 01/01/70 00:00 | |
| SDCC regression tests | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| Who's doing the hard work? | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| how totally worthless | 01/01/70 00:00 | |
| testbench vs hardware | 01/01/70 00:00 | |
| If you want to get really silly | 01/01/70 00:00 | |
I dont' think that's silly, why do you? | 01/01/70 00:00 | |
| Test against T51 at www.opencores.org? | 01/01/70 00:00 | |
| Testbenching is the answer. | 01/01/70 00:00 | |
| just think of this | 01/01/70 00:00 | |
| we're stress testing an FPGA 805x | 01/01/70 00:00 |