| ??? 01/19/06 19:38 Read: times |
#107837 - well yes Responding to: ???'s previous message |
This is one of the problems,the time required to run a testbench., and mostly they are written to log the results and so on.But yes you are right its a long winded process which is why bugs get through in new silicon,time pressure means that designs dont get fully tested before they commit to silicon.Very often designs get sent to the silicon foundry only to go back for a second run within a week or two.
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| Topic | Author | Date |
| Stress testing a synthetic 8051 core | 01/01/70 00:00 | |
| How about this one? | 01/01/70 00:00 | |
| test suite | 01/01/70 00:00 | |
| Taa daa!!! | 01/01/70 00:00 | |
| although.. | 01/01/70 00:00 | |
| link.. | 01/01/70 00:00 | |
| SDCC regression tests | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| Who's doing the hard work? | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| how totally worthless | 01/01/70 00:00 | |
| testbench vs hardware | 01/01/70 00:00 | |
| If you want to get really silly | 01/01/70 00:00 | |
I dont' think that's silly, why do you? | 01/01/70 00:00 | |
| Test against T51 at www.opencores.org? | 01/01/70 00:00 | |
| Testbenching is the answer. | 01/01/70 00:00 | |
| just think of this | 01/01/70 00:00 | |
| we're stress testing an FPGA 805x | 01/01/70 00:00 |