| ??? 01/19/06 14:42 Read: times |
#107803 - well yes Responding to: ???'s previous message |
Thats basically what you are doing with a testbench only you are not actualy running any physical hardware,just a simulation with all the timing for each net,and its used to formaly test a design before you commit to actualy producing a design in silicon for example if its for an asic/fpga.
It cannot be 100 percent acurate because there are random processes working in things like metastability but it gives a pretty good idea of how 'real' silicon will behave. |
| Topic | Author | Date |
| Stress testing a synthetic 8051 core | 01/01/70 00:00 | |
| How about this one? | 01/01/70 00:00 | |
| test suite | 01/01/70 00:00 | |
| Taa daa!!! | 01/01/70 00:00 | |
| although.. | 01/01/70 00:00 | |
| link.. | 01/01/70 00:00 | |
| SDCC regression tests | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| Who's doing the hard work? | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| how totally worthless | 01/01/70 00:00 | |
| testbench vs hardware | 01/01/70 00:00 | |
| If you want to get really silly | 01/01/70 00:00 | |
I dont' think that's silly, why do you? | 01/01/70 00:00 | |
| Test against T51 at www.opencores.org? | 01/01/70 00:00 | |
| Testbenching is the answer. | 01/01/70 00:00 | |
| just think of this | 01/01/70 00:00 | |
| we're stress testing an FPGA 805x | 01/01/70 00:00 |