| ??? 01/10/06 13:35 Read: times |
#106961 - Stress testing a synthetic 8051 core |
First of all hello to you all being my first message on the board !!!
Then I have a problem where I could use some help from the people experienced with 8051 cores synthesised in FPGA ( Xilinx), I have to work with such a beast and so far so good, I did load a lot of programs torturing it ;) and it holds, but my boss would like to have some more formal test of the whole instruction set and compliance with the actual 8051 ( the VHDL simulations are not enough, he wants a program that runs on the real hw.). While I'm by no means a novice, this task is new to me and I don't want to reinvent the wheel if there is such thing already done that you could load and let it run for a while and at the end stops and says "OK, all is well" or "Phase 54: That instruction is bad" of course as an error code in a memory location for example or output on a port. If you know of such a best I'd very much like to hear about it. Thank you for your time and kind help, Mircea |
| Topic | Author | Date |
| Stress testing a synthetic 8051 core | 01/01/70 00:00 | |
| How about this one? | 01/01/70 00:00 | |
| test suite | 01/01/70 00:00 | |
| Taa daa!!! | 01/01/70 00:00 | |
| although.. | 01/01/70 00:00 | |
| link.. | 01/01/70 00:00 | |
| SDCC regression tests | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| Who's doing the hard work? | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| how totally worthless | 01/01/70 00:00 | |
| testbench vs hardware | 01/01/70 00:00 | |
| If you want to get really silly | 01/01/70 00:00 | |
I dont' think that's silly, why do you? | 01/01/70 00:00 | |
| Test against T51 at www.opencores.org? | 01/01/70 00:00 | |
| Testbenching is the answer. | 01/01/70 00:00 | |
| just think of this | 01/01/70 00:00 | |
| we're stress testing an FPGA 805x | 01/01/70 00:00 |