| ??? 01/19/06 19:48 Modified: 01/19/06 19:53 Read: times |
#107839 - how totally worthless Responding to: ???'s previous message |
downloading the core into the FPGA and then downloading the hex-files to the "code" memory, hook up a uart and process the results
how totally worthless. sure it will discover things like add 2 to 2 does not produce 4 but it will never discover the intricacate problemss you see examples of in the chip errata for the chips we use. How is running a "random" program going to detect a problem like that if the serial and E1 interrupts happen within the same 5 nanoseconds of the instruction cycle the "chip" is gong to screw up? Erik |
| Topic | Author | Date |
| Stress testing a synthetic 8051 core | 01/01/70 00:00 | |
| How about this one? | 01/01/70 00:00 | |
| test suite | 01/01/70 00:00 | |
| Taa daa!!! | 01/01/70 00:00 | |
| although.. | 01/01/70 00:00 | |
| link.. | 01/01/70 00:00 | |
| SDCC regression tests | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| Who's doing the hard work? | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| how totally worthless | 01/01/70 00:00 | |
| testbench vs hardware | 01/01/70 00:00 | |
| If you want to get really silly | 01/01/70 00:00 | |
I dont' think that's silly, why do you? | 01/01/70 00:00 | |
| Test against T51 at www.opencores.org? | 01/01/70 00:00 | |
| Testbenching is the answer. | 01/01/70 00:00 | |
| just think of this | 01/01/70 00:00 | |
| we're stress testing an FPGA 805x | 01/01/70 00:00 |