| ??? 01/30/06 21:20 Read: times |
#108771 - testbench vs hardware Responding to: ???'s previous message |
And running an FPGA testbench simulation takes way more time than just downloading the core into the FPGA and then downloading the hex-files to the "code" memory, hook up a uart and process the results. I'm a huge fan of HDL testbenches. I did an FPGA design using a QuickLogic QL5064 device, which is one-time-programmable. At a hundred bucks a pop and longish lead times, you take the time to write detailed testbenches. Admittedly this is nowhere as expensive as an ASIC spin. Unlike SRAM-based FPGAs, you can't simply say, "OK, I want to bring out X signals to pins to hook up to a logic analyzer." OK, you CAN do that, at the cost of a chip. When writing testbenches, you need to understand your design fully so you can anticipate all of the corner cases that break things. Now, once you are convinced that your hardware passes your testbenches, then you can do the software regression tests in the actual hardware. -a |
| Topic | Author | Date |
| Stress testing a synthetic 8051 core | 01/01/70 00:00 | |
| How about this one? | 01/01/70 00:00 | |
| test suite | 01/01/70 00:00 | |
| Taa daa!!! | 01/01/70 00:00 | |
| although.. | 01/01/70 00:00 | |
| link.. | 01/01/70 00:00 | |
| SDCC regression tests | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| Who's doing the hard work? | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| how totally worthless | 01/01/70 00:00 | |
| testbench vs hardware | 01/01/70 00:00 | |
| If you want to get really silly | 01/01/70 00:00 | |
I dont' think that's silly, why do you? | 01/01/70 00:00 | |
| Test against T51 at www.opencores.org? | 01/01/70 00:00 | |
| Testbenching is the answer. | 01/01/70 00:00 | |
| just think of this | 01/01/70 00:00 | |
| we're stress testing an FPGA 805x | 01/01/70 00:00 |