| ??? 01/29/06 20:02 Read: times |
#108656 - Testbenching is the answer. Responding to: ???'s previous message |
You can write a testbench that feeds a routine that leaves registers and all addressable resources in a known state, then and feeds each and every possible opcode to the core, recording the resulting content of memory, registers, etc. Then you have to run that same procedure on a "real" 805x version of your choosing, and compare the resulting output.
Routing the addressable resource content through the UART makes it readily recordable under any of several terminal programs on your PC for subsequent automatic comparison. You can use type conversion and textio in VHDL to help produce readily readable output. That should point out any differences, which you then can fix or choose to live with them. Just for consistency with the original 805x, I'd test the code against a real 8052, however, as well as one or more of the currently available versions. I'm sure you'll find this educational. RE |
| Topic | Author | Date |
| Stress testing a synthetic 8051 core | 01/01/70 00:00 | |
| How about this one? | 01/01/70 00:00 | |
| test suite | 01/01/70 00:00 | |
| Taa daa!!! | 01/01/70 00:00 | |
| although.. | 01/01/70 00:00 | |
| link.. | 01/01/70 00:00 | |
| SDCC regression tests | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| Who's doing the hard work? | 01/01/70 00:00 | |
| well yes | 01/01/70 00:00 | |
| how totally worthless | 01/01/70 00:00 | |
| testbench vs hardware | 01/01/70 00:00 | |
| If you want to get really silly | 01/01/70 00:00 | |
I dont' think that's silly, why do you? | 01/01/70 00:00 | |
| Test against T51 at www.opencores.org? | 01/01/70 00:00 | |
| Testbenching is the answer. | 01/01/70 00:00 | |
| just think of this | 01/01/70 00:00 | |
| we're stress testing an FPGA 805x | 01/01/70 00:00 |