??? 01/30/06 18:15 Read: times |
#108760 - we're stress testing an FPGA 805x Responding to: ???'s previous message |
The OP stated he wanted to test 8051 cores synthesised in FPGA.
Here we are, once again, trying to change the definition of the problem because we can't come up with a reasonable solution. VHDL testbenches are entirely capable of testing absolutely every aspect of the model being simulated. You can, if you like, simulate the core's behavior to whatever level of detail the model is specified, and the logic is certainly going to have to be complete, in every possible internal state as subjected to every possible combination of inputs. An exhaustive test requires exactly that. However, I think you'd be surprised at how few manufacturers actually test their products exhaustively. Just look at the Pentium processor, for example, or look at Microsoft's Windows OS. Who do you know, that believes that M$ tested WindowsXP with every possible combination of internal states, RAM content, and HDD content, and every possible string of input data? They'd have had to hire a few million more test personnel, buy a few million more computers, and wait a few million years for the result. Of course, those of us who'd have waited for the result would have gotten a reliable OS, but who'd have lived that long? Because a VHDL model has to be completely specified, it can be completely and exhaustively exercised in simulation. Ultimately, of course, it has to be proven in hardware and, as you know, there are many differences between real hardware and the objective specification against which the documentation is written. VHDL testbenches enable the designer to exercise the logic by behavior. That verifies that the logic, which, of course, is not physical, behaves as designed. The implementation tools, generally provided by the programmable logic vendor or, perhaps, a well-informed third-party software tool vendor, are responsible for the details of the physical implementation of that design. Different implementation software may well produce quite different results. That's why physical testing is needed before production begins. The simulator primarily tests the validity of the logic and the synthesis. It makes predictions of the performance within the confines of a specified set of parameters. Ultimately, the implemented hardware has to be cooled, heated, loaded, etc, to meet test criteria before it can be sent to production. The OP wants to test his design, however, and that's independent of the physical hardware, at least to a limited extent. He doesn't, for now, have to heat, cool, load, or vary supply voltages or inject noise, into his design. He just wants to ensure that his logic design is soundly consistent with the 805x. A VHDL testbench can do that for him. RE |
Topic | Author | Date |
Stress testing a synthetic 8051 core | 01/01/70 00:00 | |
How about this one? | 01/01/70 00:00 | |
test suite | 01/01/70 00:00 | |
Taa daa!!! | 01/01/70 00:00 | |
although.. | 01/01/70 00:00 | |
link.. | 01/01/70 00:00 | |
SDCC regression tests | 01/01/70 00:00 | |
well yes | 01/01/70 00:00 | |
Who's doing the hard work? | 01/01/70 00:00 | |
well yes | 01/01/70 00:00 | |
how totally worthless | 01/01/70 00:00 | |
testbench vs hardware | 01/01/70 00:00 | |
If you want to get really silly | 01/01/70 00:00 | |
I dont' think that's silly, why do you?![]() | 01/01/70 00:00 | |
Test against T51 at www.opencores.org? | 01/01/70 00:00 | |
Testbenching is the answer. | 01/01/70 00:00 | |
just think of this | 01/01/70 00:00 | |
we're stress testing an FPGA 805x | 01/01/70 00:00 |