| ??? 03/31/05 20:14 Read: times |
#90773 - Many Gates? Responding to: ???'s previous message |
Erik Malund said:
No instructions, but gates to decode what RAM address the 'r' instruction should access.
Agreed, but right now they have to route two bits from the PSW to form the upper address bits of the r instruction. How many more gates would be needed to route 3 bits instead of 2? On a completely different note, I was amused by your anecdote about working out 'levels' of subroutines on an early PC. I remember reading an article on the design of the 6809 micro with a picture of the LSTTL breadboard they built to verify functionality - obviously way beyond the simulators of the day. Ian |
| Topic | Author | Date |
| Registers | 01/01/70 00:00 | |
| my guess | 01/01/70 00:00 | |
| Participation | 01/01/70 00:00 | |
| Old Age | 01/01/70 00:00 | |
| Old but stronger still | 01/01/70 00:00 | |
| just a guess | 01/01/70 00:00 | |
| Powers of Two | 01/01/70 00:00 | |
| when all was new | 01/01/70 00:00 | |
| push and pop | 01/01/70 00:00 | |
| passing | 01/01/70 00:00 | |
| Passing Parameters | 01/01/70 00:00 | |
| yes, with a monitor | 01/01/70 00:00 | |
| Register Overlaying??? | 01/01/70 00:00 | |
| Context | 01/01/70 00:00 | |
not necessarily | 01/01/70 00:00 | |
| my point was | 01/01/70 00:00 | |
| Sausages | 01/01/70 00:00 | |
| Sausage and Chips | 01/01/70 00:00 | |
| no instructions, but gates | 01/01/70 00:00 | |
| Many Gates? | 01/01/70 00:00 |