The basic 8051 needed a production test mode, since the reset pin didn't really reset the part.

Once reset is active, the PSEN and ALE pins become inputs. The original Intel data sheet stated "Driving ALE and /PSEN low while reset is active could cause the device to go into an indeterminate state." That is because they were built with dynamic logic, and stopping the clock causes all of the dynamic nodes to decay. This is not a problem with static CMOS devices.

That is as close as the data sheets got. It is NOT an officially condoned procedure. It should ALWAYS be done synchronized to the X1 input.

Doing this resets both the /2 flop on the clock input and the /6 state generator that controls the 8051 instructions. It also appears to generate a flash refresh cycle for the programming bits in parts that have flash.

The use of this circuit is common in the Intel and Philips parts. I have no knowledge about other parts.

Note that the combination of PSEN low and ALE low was also used in the programming of EPROM devices. In that case, it didn't matter that the processor was also being reset.

Again, DO NOT TRY THIS AT HOME.