| ??? 02/14/07 17:01 Modified: 02/14/07 17:11 Read: times |
#132948 - Especially difficult to design Responding to: ???'s previous message |
Erik said:
I would advise anyone against even attempting this unless ready to read and read again datasheets (how does the comparator behave when Vcc is at < 1V on the way up?) and REALLY design this thing. One surprising result of the investigation was how low a Vcc some uC start at, please do not ask for exact, it was a good while ago, but my recollection is that the occsional uC did things already at 2V. It's extremely difficult to build such a circuit. Not only because it must reliably work from Vcc=0V on, but must also withstand noise, spikes, glitches and dips on Vcc under all working conditions. This is especially difficult, because the reset circuitry mostly is an dynamically working thing, in order to guarantee a stable reset active time. Many of the older reset chips were extremely sensitive to glitches on Vcc. I remember that we had a thread "A watchdog for a watchdog?". With the MAX1232 I never had any trouble, but must confess, that I use intense Vcc filtering in my circuits, to define the rise and fall times of Vcc during power-on and power-down. Also, I use an additional pull-up resistor of 4k7 on the reset line of micro, to guarantee a proper performance at very low supply voltages. Kai |
