| ??? 01/13/07 02:49 Modified: 01/13/07 03:22 Read: times |
#130761 - Hair-raising... Responding to: ???'s previous message |
Purushottam said:
The 89C2051 datasheet says Iol is limited to 10mA per port. This statement is entirely ridiculous! There's no such built-in current limitation. Just the opposite is true: YOU must guarantee, that this limit is not exceeded, for instance by the help of current limiting resistors!! Purushottam said:
From TB62726 datasheet I found following Input specifications:
... Max clock rise time = 5uS. ... Hazman has pullup resistor of 1Kohm so risetime is 1x10^3 x 30 x 10^-12 = 30 x 10^-9 i.e. 30nS. where 30pf is assumed of micro + TB pin capacitance. Your calculation is questionable: 1. I cannot see, that the clock line sees a 1k pull-up. I can assume it, but I don't see it from the "schematic". 2. What you calculated is the time constant, not the rise time. 3. It's a well known and well proven fact, that a clock line must always be driven by a low ohmic source and by a signal providing steep edges. Rise time of clock signal of up to 5µsec MIGHT work, with a proper set-up, means a properly routed printed circuit board containing a solid ground plane AND by using a low ohmic clock signal driver. But in combination with an assumed bread board design and a true open drain driver like port0, this is the best way to make the project fail. In opposite to port0, port1/2/3 have strong internal active pull-ups (making the output drivers appear as stiff push-pulls), being activated for two oscillator periods whenever the port lines have to toggle, and guaranteeing very steep edges. Port0, on the other hand, in this critical moment presents the relative high source impedance of external pull-up resistor, which is about 1000 / 50 = 20 times (!) higher than the strong internal active pull-up, making the rising edge of clock signal especially susceptible to capacitive cross coupling (charge injection via stray capacitance). The result can be the develop of a certain ringing superimposed to clock signal. This can mean, that multiple clock edges will arrive. This IS an important failure mode of CMOS circuits and was observed and described in the literature many many times! The 4k7 pull-up you propose will result in an even higher source impedance, which is about 100 times (!!!) higher than the strong internal active pull-up of port1/2/3 lines! Read what Texas Instruments wrote about capacitive cross coupling of adjacent lines in combination with CMOS and you will see, that this is not only a theoretical weak point. I repeat, what I originally stated: Port0 lines, which consist of true open drain outputs are not at all suited to drive clock lines of shift registers and similar, unless impractically low external pull-ups are used. Use instead a port1/2/3 line, because the briefly activated strong internal active pull-up guarantees fast and clean edges. Kai |
