| ??? 07/18/07 16:09 Read: times Msg Score: +1 +1 Informative |
#142001 - Jan is close! Responding to: ???'s previous message |
Jan Waclawek said:
Who will find the next?
The explanation of EXTRAM throughout pages 13 to 14 including table 7 clearly indicate, that the internal XRAM is accessed when EXTRAM=1. Fig.4 clearly indicates, that the internal XRAM is accessed, when EXTRAM=0. Tom, try both... JW Very good! I found the same discrepancies, so we tried EXTRAM = 1, and both C51RB2 & CV51RB2 failed! But the C51RB2 & CV51RB2 both worked when EXTRAM = 0!!??! So what's going on? 1. Good 'ol NXP still doesn't know how to produce a data sheet. Fig 4 is correct. The gibberish on pages 13 & 14 is not. 2. The real bug is that AUXR is NOT cleared at reset. This is why it didn't work at first, because our original code relied on the reset value (0x00), but did work after adding in the initialization for AUXR. So there you have it. I'm sending a bug report to our local NXP rep and the NXP engineer he referenced. Mystery solved. tom |
| Topic | Author | Date |
| P89CV51Rx2 XRAM bug? | 01/01/70 00:00 | |
| @Ri or @dptr? | 01/01/70 00:00 | |
| @dptr | 01/01/70 00:00 | |
| P89v51 <--> P89C51 differences | 01/01/70 00:00 | |
| Oh sorry I mis-read | 01/01/70 00:00 | |
| What is the full part No of the C51RB2? | 01/01/70 00:00 | |
| P89C51RB2BA & internal XRAM | 01/01/70 00:00 | |
| what is "the CV51 solution" ? | 01/01/70 00:00 | |
| isp entry on /PSEN - as with the old \'C51Rx2 | 01/01/70 00:00 | |
| maybe, maybe not | 01/01/70 00:00 | |
| P89V P89C | 01/01/70 00:00 | |
| CV51 solution | 01/01/70 00:00 | |
| the old errors... | 01/01/70 00:00 | |
| OK, I found the first error in the new datasheet.. | 01/01/70 00:00 | |
| whoever wrote that datasheet... | 01/01/70 00:00 | |
Jan is close! | 01/01/70 00:00 |