... and they happen irrespective of the entry method being used.

I don't dislike HDL's ... I dislike the cost of reviews when using HDL's, and that, largely, is because the people for whom I provide services know how to read a schematic diagram, yet don't know how to interpret VHDL or Verilog, and, therefore, don't trust it. They can read and understand ASM, and even FORTRAN code, and even PASCAL, but aren't terribly comfortable with 'C' unless it's properly commented, and written with lots of the "crypticisms" that make 'C' fun for programmers, since only they can then understand what it really means.

When my clients, in the past, have hired "HDL experts" to review a design entered in HDL, they seem to get N+1 opinions for every N "experts." The result is they have little confidence in the now very costly review, since rather than taking half a day, it took half a month, not only of the costly "expert" time, but of theirs as well, since they like to witness the reviews, asking questions as they arise.

I get by with VHDL-entered components presented in a block diagram, much as you do, I suspect, but show them simulations of the components that aren't obvious as to their function.

My clients know what a counter, shift-register, or parity tree is, but they don't recognize it in HDL unless it's properly commented (sound familiar?) Those same guys can read a datasheet and understand what it says, and they learned economics from Heilbronner, Galbraith, and Samuelson, and read Kant, Schopenhauer, desCartes and Campbell and remember what the world was like when experts weren't what the Germans call Fachidioten. Many of them hold PhD's or MS's and certainly are thoroughly-educated, well-rounded individuals. They don't just accept what's popular today because it's popular.

The result is that I present documentation in a form that's palatable to them to the extent that it's possible. The "schematic" that's conjured up by the software from HDL isn't often a readable or understandable schematic, as it's often configured in an unrecognizable way. It certainly isn't what my clients are used to seeing.

A "real" gate-level schematic is what I like to present, though it's often necessary to resort to block diagrams with supportive simulations. That's largely because I've been doing it that way since the '60's, and old habits are hard to break.

RE