The latches that were used in place of clocked registers in early, but very functional, designs such as the 6800 and 6502 were used because (A) they require no setup time, and (B) they are essentially ONE gate rather than six. Since the 805x core was designed at about the same time as these guys were extremely popular, I'd not be surprised to find many of them in the "real McCoy."



You once mentioned your 805x implementation as one that "almost" worked, still having problems with interrupts, or some such. There are lots of "almost" complete 805x's out there, none of them very fast, or very complete, and if this guy has a version that works as well as yours, I'd not be jumping on him because he used a few latches.

VHDL is a great way of getting from a set of known behaviors to an implementable design, but it seldom produces a result that is as efficient as a hand-tweaked gate-level schematic. Unfortunately, the tools we have to use today translate that hand-tweaked gate-level schematic into an inefficient VHDL or, in some cases, Verilog, equivalent that is just a inefficient as the one synthesized from VHDL or Verilog source.

I wouldn't give up on HDL's to create designs from precise spec's, but that's because it imposes structure, not because it's the most efficient implementation. It is, however, probably the most effective use of man-hours, but not of silicon.


RE

Edited: I mistakenly said hold time, where I meant setup time in the italicized item above.

BTW, I don't feel that this presentation makes it easy, in any sense, to understand the workings of the 805x core.