| ??? 06/20/05 16:37 Read: times |
#95376 - Fundamental flaw Responding to: ???'s previous message |
The trouble with the ZE5 (nee TE5), of course, is that it isn't a single-chip solution - because you require an external flash, or other external programming arrangement.
But then so do many FPGAs - so having the FPGA and processor in a single chip does still reduce the chip-count. |
| Topic | Author | Date |
| ASIC '51s and speed | 01/01/70 00:00 | |
| Zylogic? | 01/01/70 00:00 | |
| probably not | 01/01/70 00:00 | |
| why not look.. | 01/01/70 00:00 | |
| Details please? | 01/01/70 00:00 | |
| Details | 01/01/70 00:00 | |
| T51 limitations | 01/01/70 00:00 | |
| t51 limitations,not quite | 01/01/70 00:00 | |
| so running from RAM | 01/01/70 00:00 | |
| TCL and all that | 01/01/70 00:00 | |
| other case, probabl same answer | 01/01/70 00:00 | |
| very interesting! | 01/01/70 00:00 | |
| Advantages of single-chip | 01/01/70 00:00 | |
| Fundamental flaw | 01/01/70 00:00 | |
| Final thought | 01/01/70 00:00 | |
| use two | 01/01/70 00:00 | |
| better one superfast | 01/01/70 00:00 | |
| Pitfall? | 01/01/70 00:00 | |
| Multi cpu pitfalls | 01/01/70 00:00 | |
| Hardware delegation? | 01/01/70 00:00 | |
| 2 questions | 01/01/70 00:00 | |
| Why are you obsesed with zylogic? | 01/01/70 00:00 | |
| Obsessed? moi! | 01/01/70 00:00 | |
| well | 01/01/70 00:00 | |
| Thanks, but no thanks | 01/01/70 00:00 | |
| uPSD | 01/01/70 00:00 | |
| sorry, no | 01/01/70 00:00 | |
| FYI - Hitex 8051 SoC kit | 01/01/70 00:00 | |
nice, will check | 01/01/70 00:00 |