DRAMs are not so difficult that I don't think of them from time to time.

I frequently use 64kx4 (18-pin) or 256Kx4 (20-pin) DRAMs when I can because of their density and because I don't have to route as many addresses. There's even a "hidden refresh" mode that exploits the internal refresh counter in the majority of CMOS DRAMs, though I've never used it. I've got LOTS of these devices sitting around in a box of laser printer memory cards left over from when I had several HP laserjet printers in operation.

This shift-register-based timing scheme was thought up by a friend of mine back in the '70's, when I was still using delay lines to time the control strobes. As it happens, he was using a 12 MHz clock to drive the shift register with a processor that operated at 1 MHz, so the timing is very similar to what's produced by a 12 MHz 805x (12-clocker). I've never attempted this with an 805x using its crystal oscillator, but there's really no reason why X2 shouldn't be able to drive an external buffer or single CMOS device. At most, one might want to compensate for the added capacitance of the buffer/shift-register, by reducing the "burden" cap by, say, 5 pf.

The latch on P0 should be enabled on positive nRAS so an inverting gate is required, and the latch on P2 should be enabled on negative nRAS. The refresh nRAS falling edge should be at least two clocks after the rising edge of the memory cycle nRAS rising edge, to allow for the nRAS-recovery.

It might be a good idea to use (/nWr * /nRD * /Qg) as nCAS, but the tiing is so generous at 12 MHz, that one shouldn't have to worry the odd ns here and there.

Remember, simply, that row addresses must be stabile at the DRAM at the falling edge of nRAS, and column addresses must be stbile at the falling edge of nCAS. nWE must precede nCAS in order to perform an "early write" cycle which prevents data bus contention. A 12 Mhz clock is plenty long to allow all this to operate with a minimum of risk.

Go ahead! Give it a try ... build the logic and examine the resulting signals with your 'scope or logic analyzer. Satisfy yourself that DRAM requirements are met.

RE