Oddly enough, I have the old databook right here. Assuming (perhaps incorrectly) that you know what these are, and have the signal definitions, I can summarize the basic operation in not too many words.

There are three control signals, nRAS, nCAS, and nWE. Some (2 or 3-chip) SIMMs have an nOE signal also, but those are very uncommon.

Assuming that you're using the signals and data bus timing from an 805x, you can do the following.

AND (negative logic OR) nRD and nWR by using the two data inputs on a 74HCT164. Connect the '164's Qa output to nRAS, the Qb output to an OR (negative logic AND, 74HCT32) the other input of which gets nWE, and Qc to nCAS. Connect the CLOCK input of the '164 to a buffer driven by the X2 (output) of the oscillator of your 805x (You've provided little information, so I assume you're using a 12x-clocked MCU). Now apply the latched address bus to the inputs of two 74HCT257's. These are multiplexers, and will apply eight addresses to the DRAM some of the time, and the other eight the rest of the time. If you want to use more than 64KB of the memory space, you'll have to get more address lines from somewhere. The select input of the multiplexers is driven with the nRAS signal. The nWE of the DRAM SIMM is driven with the output of the 74HCT32. An external bus cycle is 6 clock ticks long, of during only four of which the signals I use here are present. That cycle on a 12 MHz MCU takes about 250 ns. If you then take delaued nRAS from Qg and use the rising edge of that clock to drive the counter of a 74HC590, with its nOE tied to Qg, that will provide a refresh cycle. I'll leave it up to you whether you want to save a bit of power by only refreshing when necessary.

It doesn't matter at all how you order the address and data I/O.

RE