It was very late when I wrote the DRAM description above. I left out the refresh timing, which is very simple and based on the same logic.

Actually, the '257's could be omitted, and simply replaced by output enables on the address latches, assuming, of course, that both P0 and P2 have '373/'573 address latches attached. Their outputs should be commoned, and also commoned with the outputs of the '590. The '590 output enable and CCLK should be tied together, which causes the counter to count on the rising edge of active-low output enable. The outputs of the two address latches should be tied together at the MA[7..0] inputs of the SIMM, and it might be better than what I originally suggested if Qa of the '164 were negative-logic-ANDed (74xx32) with nWr to generate nWE to the DRAM.

You COULD omit the '590, and use a regular interrupt to perform the refresh, requiring simply that the MCU read a location the LS byte of which is an 8-bit strictly increasing counter. That's more or less what the folks at IBM-Boca Raton did with the original PC. They used approximately 15625 Hz as a refresh rate. If a 5 MHz PC could tolerate that, it's likely that a 12 MHz 805x in a not-too-taxing job could tolerate it as well. The refresh period on the original PC required a 256-refresh cycle period of 2 ms. CMOS Drams, as were popular by the time they were packaged in SIMMs, used a 4 ms refresh period.

The whole timing scheme, based on the X2 output from the MCU, falls apart at rates much above 18 MHz, BTW, depending, of course, on the performance specification of the DRAMs. Remember, there must be a RAS-recovery time equal, typically to the access time of the DRAM. That's why the cycle time is essentially twice the access time of a DRAM.

The important things to keep in mind are as follows.

(a) Setup time for addresses before falling edge of nRAS and nCAS is typically 0. It can't be less, but 0 should work. I've never relied on this and always added at least one gate delay.

(b) asserting nWE before nCAS ensures that there will be no data output. That eliminates the need for an output enable.

(c) a Refresh cycle is just like any other cycle, with the exception that there is no column address or data traffic. Whenever an address is applied and nRAS asserted for at least the minimal time, all the cells in that ROW are refreshed at the rising edge of nRAS. That's why the nRAS-recovery-timer is required.

The reason I have submitted this simple description is not to suggest it is perfect or complete for any particular purpose, but, rather, to show that DRAMs are really quite simple, which, along with their low cost per bit, is what led to their overwhelming popularity in the late '70's.

I'll attempt to put a schematic that reflects more attention to detail and correct timing on my personal web page on this site as soon as I can.

RE