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???
06/14/07 07:04
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 		 #140741 - interrupt latency
Responding to: ???'s previous message
I think the interrupt latency will completely obliterate this idea.

List of 28 messages in thread
TopicAuthorDate
10mhz clock from 8051 cpu            01/01/70 00:00      
   BARELY possible ...            01/01/70 00:00      
      Ten milli hertz - that's a doddle!            01/01/70 00:00      
         SynMOS            01/01/70 00:00      
            what's MIP?            01/01/70 00:00      
            What, exactly, do you mean?            01/01/70 00:00      
      if you don't mind WHICH pin it is...            01/01/70 00:00      
         I think he does            01/01/70 00:00      
            well if that data does not need to change...            01/01/70 00:00      
               how are you going to get the data to "any pin"            01/01/70 00:00      
                  one instruction cycle            01/01/70 00:00      
                  DS89C4x0 might manage it            01/01/70 00:00      
                     let's have a 'yellow light'            01/01/70 00:00      
   graphical display            01/01/70 00:00      
      so you do NOT need just a clock            01/01/70 00:00      
         10MHz clock from 8051            01/01/70 00:00      
            Consider what you\'re doing.            01/01/70 00:00      
               SiLabs F120            01/01/70 00:00      
                  Are you certain that applies?            01/01/70 00:00      
                     I specifically did not            01/01/70 00:00      
                        that's true ...            01/01/70 00:00      
                           then why7 the ^&%$&^(* are we discussing that?            01/01/70 00:00      
                              You're absolutely right, Erik ... We need input.            01/01/70 00:00      
               nonsense?            01/01/70 00:00      
                  Little nonsense is better            01/01/70 00:00      
                     not 'a little' but 'utter' nonsense            01/01/70 00:00      
                     interrupt latency            01/01/70 00:00      
                        Maarten, you are correct            01/01/70 00:00      

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