You are assuming that the high voltage limit is to prevent SCR latch-up. This is probably not the reason for the voltage limit.

In advanced CMOS processes, the voltage limit is to prevent damage to the gate oxides used in the circuit. I won't go into the physics, but stressing a gate causes some gates to become "leaky". And once a gate starts being leaky, then is more easily damaged by future over-voltage stresses.

And while the leakage might not be enough to cause a logic failure, it can certainly cause stuck bits in RAM, or cause a flash bit to discharge in days rather than years.

Over-voltage hurts the reliability of the part. Your system will work well at first, but fail later in your customer's hands.

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Most CMOS circuits are made on an epitaxial process, which pretty much eliminates the possibility of an SCR failure.