Yes, that's the way most dilletantes do it. You hook up something, then try to guess why it doesn't do what you imagine it should.

While I believe the OP will have no luck with any of the, by now, quite amateurish OrCAD tools, since nobody at OrCAD/EMA/Cadence really builds complex models for its simulators, I can see why he might want to do that.

While I have, at least once, seen a relatively "professional" tool, namely HILO for UNIX, that had microprocessor models, their implementation was barely effective, and that was about 20 years ago. Sadly only the most sophisticated/costly tools allow one to simulate both microcontrollers and "family" logic.

The tools used in FPGA modeling seldom support external logic, and simulation of logic to be implemented in FPGA might help one find the occasional logic error, it won't provide useful information about timing issues in circuitry implemented physically in discrete MCU + discrete SSI/MSI logic.

Sadly, low/no-cost tools for programmable logic don't allow mixed vendors, and they don't support SSI/MSI logic implementations. One could fiddle with the timings in the simulation model for each type of gate and possibly approach a good approximation, and that's all that a simulator can provide, for each logic device in the circuit, I doubt it would be productive over the long run.

Somewhere, there's probably a purely behavioral simulator that would support modeling an 805x core. With as many differnt versions/implementations of that core, however, it's unlikely one would even get a reasonable approximation of the resulting timings, and, if one could, it would be difficult to approximate how the behavior would vary over variations in temperature, loading, power supply variation, etc.

If somebody has a SPICE model of this or any other MCU, I'd be very interested in seeing it.

In the meantime, it's also worthwhile to consider what OrCAD once offered in their design tool suite. They had a simulation tool called VST, (verification and simulation tool) that worked well with their SDT (schematic design tool) which was their very popular and extremely useful DOS-based schematic entry tool. Later, after their success with their SDT, they acquired VST and attempted to support it with a user interface similar to what SDT used, and they acquired PCB, and, likewise, tried to cobble a very similar user interface for it, both with some, though not complete, success. SDT was quite nearly perfect, but VST had a couple of fatal bugs, and PCB's user interface was plagued with repeated and counterintuitive operations which made it slow and awkward. OrCAD then produced their ESP shell, which was intended to integrate their v4.x software flows under a common environment. They also acquired MicroSim, the producers of PSpice, an EXCELLENT simulator. This precipitated a move to Windows (then it was Windows 3.x). In the course of that shift they lobotomized SDT, discarded VST, and, in parallel, developed a very good set of 386-compatible tools for DOS. The Windows verison(s) have never made it to genuinely useful quality, though they're widely used.

Today, it takes weeks of late nights using the Windows-based tools to generate schematics that take less than half a day using the DOS-based tools.

The VST simulator is completely behavioral, while the PSpice simulator uses very precise mathematical models, even for digital hardware. If someone were to generate a PSpice model for an 8052, I'd be happy to use it, but I doubt anyone would take the time. Given a tool such as that, and combined with models for the sort of family-logic commonly used with MCU's, one could readily simulate a microcontroller-based circuit given a set of external ROM code. I doubt it would be easy to do the same thing with internal ROM code, however.

RE