The JTAG specification (IEEE1149) requires that the JTAG state machine could be placed into so called BYPASS mode (it then behaves more-less as a 7474 while only TDI-TDO-TCK is used (state transitions are initiated using the TMS pin)). The description how to do it is also compulsory and is contained in the associated .bsd file. It means that there can be any number of any vendor's chip in the chain, as long as you have the bsd files for each of them (and the "massager" is not the stupidest one), it is always possible to put all the chips except one into a state as if they would not been there.


I don't know what is "EC adapter" and what is the "processing" it includes, but it would be silly from SiLabs not to support STAPL/JAM file generation for programming (which would allow programming using independent software/JTAG chain driver hardware).
Here is the reasoning:
The JTAG interface for debugging/programming is impractical as it uses up 4 pins which have to be dedicated to this function by specification (although many manufacturer like to violate this specification and share the pins, leading often to troubles); for microcontroller it is much better to either use some proprietary one-wire interface (such as the Z8's and some ATMega's), or to use an existing interface on the mcu which would then run in a special mode (such as the UART ISP in the 'RD2's.); or to have somthing which is implemented in hardware in a much more simple and straighforward way - namely SPI (such as the AT89Sxx and P89LPC9xx and AVRs and probably many more). Usage of JTAG is justified only if more devices on the board have it, but then it is very common to test and "burn" the board and the devices using some specialized test equipment - so it would be more of a limitation if the chip would not support programming file (STAPL/JAM) generation (and of course standard boundary scan).

Jan Waclawek