| ??? 09/06/05 16:37 Read: times |
#100701 - why JTAG? Responding to: ???'s previous message |
hi,
Does Xilinx not provide another interface to download configuration into CPLD? For example, Altera ACEX1K provides some ways: JTAG, serial shift and parallel loading. JTAG is complex interface/protocol and in most cases it is not necessary no utilize it without good reason. My current project uses SiLabs C8051F120 connected to ACEX1K50 via serial downloading and does simple bit-by-bit transfer of configuration file generated with Altera software. Look at Xilinx datasheet for alternative configuration. Regards, Oleg |
| Topic | Author | Date |
| Using 8051 to program CPLD via JTAG | 01/01/70 00:00 | |
| Eh??? | 01/01/70 00:00 | |
| Reply | 01/01/70 00:00 | |
| Don't hurt yourself | 01/01/70 00:00 | |
| Ouch! | 01/01/70 00:00 | |
| Regarding XAPP058 | 01/01/70 00:00 | |
| ????????????????? | 01/01/70 00:00 | |
| It's a interpreter of XSVF | 01/01/70 00:00 | |
| why JTAG? | 01/01/70 00:00 | |
| Yes, but... | 01/01/70 00:00 | |
| not seeing the forest for the trees or w | 01/01/70 00:00 | |
| Several reasons... | 01/01/70 00:00 | |
| CPLD programming | 01/01/70 00:00 | |
| programming Xilinx CPLDs | 01/01/70 00:00 | |
| XSVF Executor! | 01/01/70 00:00 | |
| XSVF Executor | 01/01/70 00:00 | |
| XSVF Executor | 01/01/70 00:00 | |
| Using 8051 to program CPLD via JTAG | 01/01/70 00:00 | |
Yeah well | 01/01/70 00:00 |