| ??? 12/22/08 06:44 Modified: 12/22/08 06:46 Read: times |
#161098 - That was specifically noted Responding to: ???'s previous message |
Joe Gold said:
Simply quoting the NXP data sheets ( bible ) can be incorrect, depending on the part.
The new 80c51 cores of Si Lab, NXP and others have "typically" 1 and 2 clocks per instruction. Yes, and I specifically noted that fact: I said:
The answer for the "standard" 8051 architecture can, of course, be found in the so-called "bible" for the 8051 ... The Datasheet for your particular device will tell you where it differs from the standard. And, as Erik says, they are not simply datasheets for some specific chips - they are a description of the 8051 architecture in general. |
| Topic | Author | Date |
| instruction cycle | 01/01/70 00:00 | |
| bible time? | 01/01/70 00:00 | |
| Read doc's | 01/01/70 00:00 | |
| He did | 01/01/70 00:00 | |
| Apologies | 01/01/70 00:00 | |
| bible can be incorrect | 01/01/70 00:00 | |
| "the bible" is gospel | 01/01/70 00:00 | |
| That was specifically noted | 01/01/70 00:00 | |
| understood | 01/01/70 00:00 | |
ADuC841 is a single-clocker | 01/01/70 00:00 |