| ??? 04/26/07 14:33 Read: times |
#138034 - Yes ASIC design fixed... Responding to: ???'s previous message |
...and priority interrupts are also available.
Yes it is the same project I was working on before. And yes, I can manage the serial interrupt. Just as wrote in the previous threat, came this idea from the design team (and they are not such newbies as I am they have several projects behind them). So my colleagues can remind some bugs really hard to track down just because of interrupt pitfalls (ok so maybe, they are not as big Batmans as you guys). And now with an ASIC nearly without any debug possibility on SW level.... So I wanted to verify this discussion and make my own opinion. That's how this question came. So thanx much for the inputs. greetings Attila |
| Topic | Author | Date |
| Serial transmission in scheduller instead of int | 01/01/70 00:00 | |
| danger, maybe, loss of efficiency YES ABSOLUTELY!! | 01/01/70 00:00 | |
| avoiding interrupts means... | 01/01/70 00:00 | |
| Scheduller.... | 01/01/70 00:00 | |
| there is no such thing | 01/01/70 00:00 | |
| Limitation API | 01/01/70 00:00 | |
| API? | 01/01/70 00:00 | |
| Yes ASIC design fixed... | 01/01/70 00:00 | |
| debug possibilities? | 01/01/70 00:00 | |
Monitor is nice idea | 01/01/70 00:00 | |
| 1ms vs 1.04ms | 01/01/70 00:00 | |
| absolutely NOT | 01/01/70 00:00 | |
| ok but 1 byte is transmitted together | 01/01/70 00:00 | |
| if it does, then you need to KISS | 01/01/70 00:00 | |
| I took the 1ms processing tick for granted... | 01/01/70 00:00 | |
| Thanks for the inputs... | 01/01/70 00:00 |