What you're doing in this mode is creating an ASIC from an MCU. It can do only one thing, and even that may require multiples. However, if you can come up with one, or a pair, or even three, that converts refresh memory content to pixels, which it shoves out a pin, and maintains proper control timing, meaning proper sync and blanking signals, then all you have to do is use yet a another one, synchronized to that one, to control the refresh memory content. If MCU #2 only writes to the shared refresh RAM during blanking, you won't perturb the display. With an 805x, it's going to be somewhat difficult to work out the timing, but with a nominally 12 MHz clock, it shouldn't be difficult to come up with a video rate dot clock, and derive sync and blanking timing from that. It is easier with other architectures, though.

The SX ones I've seen on the PIC list, however, do only one thing, and do it all internally.

RE