The CPU's you mention did, indeed, operate from oscillators slower than the 805x. However, the 6502, with a 1 MHz clock, was easily demonstrated to do some things faster than the 8051, with a 12 MHz clock. The Z80A, quite common in 1980, was frequently contrasted with the 1 MHz 6502, owing to its popularity in various S-100-based machines, vs the 6502 in the Apple-][. Now, by 1981, the 6502 was available in versions capable of up to 4 MHz and beyond, and, by that I mean the 6502, not some slightly divergent variant.

What's critical with video is the pixel rate, and what this CPU clock rate refers to is the rate at which the CPU can access memory, which it does in BYTEs.

I don't believe I ever saw an MCU before the various devices shown on the "PIClist" some of which used the SX, that produced the pixels, AND the video timing, directly within the device, and without the aid of an external shift-register into which bytes were loaded for purposes of their disassembly into pixels.

Don Lancaster wrote a series of "Cheap-Video" Cookbooks in which he described ways of generating the video timing with a 6502.

Because the 6502 used a symmetrical clock that was invariant in its phase with respect to internal operations of the CPU, two of these could be made to work in concert, with one generating the timing and processing the bytes in the refresh memory in phase with the still external video hardware while the other CPU ran on the oppsite phase, thereby accessing the refresh memory at a time when it wouldn't cause interference with the display. This is very different from what was done in the PIC/SX example that started this thread.

While I doubt that it's been done with exhaustive completeness, yet, I don't doubt that an 805x can do this. However, it's less 805x-like than most other tasks I see on this forum, as it's more difficult to synchronize an 805x with a task operating at an externally controlled rate close to the instruction rate of the 805x than, say, a 6502, though the, now much higher, execution rates of modern 805x scions may, in fact, bring it off with their larger memory and greater speed.

As I said before, it might be achievable with the mode-0 serial port as a shift register. That, of course, depends on the relationship between the serial channel's rate and the instruction execution rate. If the write-to-display-memory routine is precisely synchronized with the write-to-serial-port routine, and the shift clock is, in fact, the dot-clock of the video subsystem, then it's likely this task can be brought off cleanly. However, keeping the sync-generation and blanking controls properly timed might make this quite challenging.

RE