Andy is right; more information is needed, as your question is unclear. In the meanwhile, I'll provide a little background.

Note that a reference ISP circuit for the device is provided in figure 15-2 on page 133 of the Ultra-High -Speed Flash Microcontroller User's Guide. According to figure 15-1 on page 132, there are three conditions that must be met simultaneously to place the '420 in ISP mode:

• RST = 1
• /EA = 0
• /PSEN = 0

The reference circuit implements exactly this. Note that /EA, during ordinary operation running from internal flash, must be high; this fact is leveraged to facilitate direct connection of the level-translated DTR signal to /EA. RST, on the other hand, must be 0 during normal operation. In addition to serving as a reset control input, on the '420, RST serves as an output to reset other components of the system when relying on the micro's internal reset logic. The use of a tri-state buffer, rather than simply an inverted version of the level-translated DTR signal, allows this functionality to still be available when the ISP hardware is present. Finally, /PSEN is an output during ordinary operation, so use of a tri-state buffer allows it to function undisturbed during normal operation.

Note that the '125 is a four-gate device. Since this circuit only requires two of them, two will remain available for other tasks.

--Sasha Jevtic