its not synthesisable but could be used to model propagation delays in a buffer.

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY TRIBUF_fifocntrl IS
    GENERIC (
        ttri: TIME := 1 ns;
        ttxz: TIME := 1 ns;
        ttzx: TIME := 1 ns);
    PORT (
        in1 : IN std_logic;
        oe  : IN std_logic;
        y   : OUT std_logic);
END TRIBUF_fifocntrl;

ARCHITECTURE behavior OF TRIBUF_fifocntrl IS
BEGIN
    PROCESS (in1, oe)
    BEGIN
        IF oe'EVENT THEN
            IF oe = '0' THEN
                y <= TRANSPORT 'Z' AFTER ttxz;
            ELSIF oe = '1' THEN
                y <= TRANSPORT in1 AFTER ttzx;
            END IF;
        ELSIF oe = '1' THEN
            y <= TRANSPORT in1 AFTER ttri;
        ELSIF oe = '0' THEN
            y <= TRANSPORT 'Z' AFTER ttxz;
        END IF;
    END PROCESS;
END behavior;