| Getting Started With FPGAs | | 01/01/70 00:00 |
| A Book | | 01/01/70 00:00 |
| Proceed with caution! | | 01/01/70 00:00 |
| This is quite a nice deveolpment board | | 01/01/70 00:00 |
| I like this board | | 01/01/70 00:00 |
| I\'ve got one of these and can\'t recommend it | | 01/01/70 00:00 |
| What are you talking about | | 01/01/70 00:00 |
| Let me explain ... | | 01/01/70 00:00 |
| generaly speaking | | 01/01/70 00:00 |
| Damn, Jez, you need a spell-checker! | | 01/01/70 00:00 |
| HDL-based design needs TEST BENCHES | | 01/01/70 00:00 |
| I use 'em all the time, but ... | | 01/01/70 00:00 |
| If your design is so simple | | 01/01/70 00:00 |
| What\'s important is the entry effort | | 01/01/70 00:00 |
| I dunno where you get these ideas from Richard | | 01/01/70 00:00 |
| Can you say ModelSim? | | 01/01/70 00:00 |
| Wrong | | 01/01/70 00:00 |
| Well, the schematic needs a little work | | 01/01/70 00:00 |
| more work? | | 01/01/70 00:00 |
| a few points ... | | 01/01/70 00:00 |
| ... | | 01/01/70 00:00 |
| HDL vs Schematics, take 1E6 | | 01/01/70 00:00 |
| Thta may be great comfort to you ... | | 01/01/70 00:00 |
| Schematics? You're kidding! | | 01/01/70 00:00 |
| No, nor is my customer. | | 01/01/70 00:00 |
| both are a 'representation of Boole' | | 01/01/70 00:00 |
| Yep, you're right... | | 01/01/70 00:00 |
| To Clarify | | 01/01/70 00:00 |
| schematic as equivalence check | | 01/01/70 00:00 |
| Manual verification impossible because ... | | 01/01/70 00:00 |
| schematic verification | | 01/01/70 00:00 |
| Some more clarification | | 01/01/70 00:00 |
| hanging problem | | 01/01/70 00:00 |
| so will your post be | | 01/01/70 00:00 |
| it's not fear of the unknown, but fear of its cost | | 01/01/70 00:00 |
| Static Timing Analysis and those "young engineers" | | 01/01/70 00:00 |
| It's a sign of the times, I suppose | | 01/01/70 00:00 |
| And times change | | 01/01/70 00:00 |
| senior? | | 01/01/70 00:00 |
| That's because you've been avoiding the subject | | 01/01/70 00:00 |
| I agree entirely. test benches are a pain but | | 01/01/70 00:00 |
| Update from the OP | | 01/01/70 00:00 |
| It's true ... we see things differently | | 01/01/70 00:00 |
| the first buuk for any such venture | | 01/01/70 00:00 |
| FPGA boards and that Cypress book | | 01/01/70 00:00 |
| This may answer your question(s) | | 01/01/70 00:00 |
| some of the references in the fpga faq | | 01/01/70 00:00 |
| Good attitude | | 01/01/70 00:00 |
| Also remeber to look at webistes like www.xilinx.c | | 01/01/70 00:00 |
| My recommendation and opinions | | 01/01/70 00:00 |
| I would stay away from Virtex-II | | 01/01/70 00:00 |
| If you're going to fiddle with the 805x core ... | | 01/01/70 00:00 |
| Something about life-cycles | | 01/01/70 00:00 |
| No doubt about it. | | 01/01/70 00:00 |
| useful work | | 01/01/70 00:00 |
| Well, I beg to differ. | | 01/01/70 00:00 |
| salient point | | 01/01/70 00:00 |
| There's an area where that's not necessarily true | | 01/01/70 00:00 |
| FPGA Editor | | 01/01/70 00:00 |
| Not necessarily | | 01/01/70 00:00 |
| It's still too costly | | 01/01/70 00:00 |
| Thanks to all | | 01/01/70 00:00 |
| Update #2 from the OP | | 01/01/70 00:00 |
| A testbench is... | | 01/01/70 00:00 |
| I C | | 01/01/70 00:00 |
| test bench | | 01/01/70 00:00 |
| Makes sense | | 01/01/70 00:00 |
| Yeah but... | | 01/01/70 00:00 |
| Tristate buffer with propagation delays | | 01/01/70 00:00 |
| Schematics vs. HDL | | 01/01/70 00:00 |
| In a nutshell | | 01/01/70 00:00 |
| it\'s been a while | | 01/01/70 00:00 |
| Yes, but ... and there's always a but ... | | 01/01/70 00:00 |
| Yep you can its called gate level design | | 01/01/70 00:00 |
| Its really nothing to do with showing off | | 01/01/70 00:00 |
| did you paraphrase this? | | 01/01/70 00:00 |
| Jez, It\'s not \"sea of gates\" design, you know ... | | 01/01/70 00:00 |
| Richards, it is there philosophy | | 01/01/70 00:00 |
| Viewlogic | | 01/01/70 00:00 |
| it is true | | 01/01/70 00:00 |
Here you go Richard graphical design exploration | | 01/01/70 00:00 |
