Unfortunatly there is a lack of simulators which are cycle acurate for any given cpu.At present I have kind of got around the problem by the use of a TCL front end for a 8052 VHDL model running in a testbench in modelsim.Its slow and clunky BUT it is accurate down to individual clock cycles and you can see all the data transfers rather than just being presented with a black box where you have no idea where the data transfers occur during each machine cycle.Until someone writes a simulator which accuratly models the register transfers on a cycle by cycle basis its the only way to get an accurate simulation.