| ??? 03/17/05 00:12 Read: times |
#89829 - do not multimaster Responding to: ???'s previous message |
Your scheme sounds like multimastering, and that is always a pain. Two ideas come into mind, but I admit, both need to elaborate. First, implement bus arbitration by protocol - either using a master/slave scheme with master periodically polling, or a token passing method. Both can achieve big gross data transfer rates but both will suffer from latency - the implementation together with the requirements of the application determine, if latency is acceptable. The second idea is simpler, make two single-direction bus 4-bit-nibble-wide data (plus 2 control each - strobe and acknowledge). Tons of fun... :-) Jan Waclawek |
| Topic | Author | Date |
| Contemplating multiprocessor | 01/01/70 00:00 | |
| fifo | 01/01/70 00:00 | |
| and also | 01/01/70 00:00 | |
| multiprocessor communication | 01/01/70 00:00 | |
| ACKs | 01/01/70 00:00 | |
| You want it all and you want it for free | 01/01/70 00:00 | |
| Why not HW I2C or SPI | 01/01/70 00:00 | |
| Why not HW I2C or SPI | 01/01/70 00:00 | |
| USB ??? | 01/01/70 00:00 | |
| USB !!! | 01/01/70 00:00 | |
| USB | 01/01/70 00:00 | |
| You Correct Sir | 01/01/70 00:00 | |
| USB != I2C | 01/01/70 00:00 | |
USB > I2C | 01/01/70 00:00 | |
| do not multimaster | 01/01/70 00:00 | |
| hmm | 01/01/70 00:00 | |
| concurrence | 01/01/70 00:00 | |
| This is why | 01/01/70 00:00 | |
| depends on data rate | 01/01/70 00:00 | |
| Normally | 01/01/70 00:00 | |
| Are You Sure | 01/01/70 00:00 | |
| I would be | 01/01/70 00:00 | |
| I would be | 01/01/70 00:00 | |
| it works for me | 01/01/70 00:00 | |
| Are You Sure | 01/01/70 00:00 | |
| IIC speed - no limit | 01/01/70 00:00 | |
| nixed by other team members | 01/01/70 00:00 | |
| Multi-Proc Xface | 01/01/70 00:00 | |
| exactly | 01/01/70 00:00 | |
| Shift register (Mode 0)? | 01/01/70 00:00 | |
| Time savers | 01/01/70 00:00 |



