What you are trying to do is do-able but you need to be aware that the two processors are essencialy asyncronous to one another and so in order to transfer the data between what are 2 clock domains you need an asyncronous fifo which can be clocked be two indepenant clocks,one for the read and one for the write.
Asyncronous fifos are notoriously difficult i would recommend you look at the asyncronous vhdl fifo in the memory library i posted in the hardware section